当前位置： >>
Micron DDR3的PCB设计指导
High-Speed PCB Design ConsiderationsFebruary 2004 Technical Note TN1033IntroductionThe backplane is the physical interconnection where typically all electrical modules of a system converge. Complex systems rely on the wires, traces, and connectors of the backplane to handle large amounts of data at high speeds. The communications between the various backplane modules depends on the inherent electrical characteristics such as impedance, capacitance, and inductance derived from connectors, trace lengths, vias, and termination, to name a few. An extremely important factor for a distributed-load, high performance backplane is a basic understanding of the design practices used to ensure good signal integrity. This technical note examines some basic differences in interconnection topologies. It describes the various issues that should be considered while designing a backplane and focuses on the critical aspects of point-to-point transmission lines that are run through a backplane. These aspects include PCB line structure, vias, device packaging and backplane connectors. A PCB design checklist is provided to aid the designer. Some frequency speci?c discussion and guidelines are given. This document also discusses Lattice Semiconductor's FPSC product line and it's high-speed backplane interfaces. These provide serial streams up to 3.7 Gbps through CML differential buffers.Backplane Topology and OverviewThree different system interconnection topologies are normally used in backplanes today. These are multi-point, multi-drop and point-to-point. Traditionally systems have used multi-point/ multi-drop connection topologies, which provided ef?cient interconnection and communication between multiple devices, with a single net (node), as shown in Figure 1. Figure 1. Multi-Point Backplane IllustrationTxRxTxRxTxRxUnfortunately, this net structure provides serious data-rate limitations. Each net contains tees or branches at each point where the card connects to the backplane. These tees provide transmission line discontinuities and mismatches along the backplane signal path. The result is large signal re?ections occur at every card to backplane interface. These re?ections can propagate back and forth for substantial time periods and severely degrade signal integrity at higher speeds. Acceptable signal communication is normally achieved by waiting for the re?ected signals to settle out, for each bit of transmitted data. This imposes signi?cant speed limitations. For this reason multipoint and multi-drop backplane topologies generally have speed limits below 100 Mbps. This limit can easily drop below 10 Mbps as physical line lengths and the number of card slots increase. The point-to-point interconnection topology eliminates the signal path branches described above. The resulting signal re?ections are eliminated and maximum data rates are increased dramatically. This type of backplane interconnection can be used with data-rates to 3 Gbps and above, with careful design methods.? 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speci?cations and information herein are subject to change without notice.www.latticesemi.com1tn1033_03Lattice SemiconductorHigh-Speed PCB Design ConsiderationsThe disadvantage of this approach is an increase in the number of backplane nets and card port interfaces that may be needed. The single net connection between n cards, in a multi-point backplane, must be replaced with n(n1) unidirectional point-to-point links. Each card must provide n-1 transmit and n-1 receive ports for full system interconnectivity. As an example, a four PCB module system with full interconnectivity is shown in Figure 2. Figure 2. Four Card Point-to-Point Interconnection System Card 1 Card 2Card 3Card 4Each card must provide 3 transmitter and 3 receiver ports. Each arrowed line represents a point-to-point backplane net. Recent communications equipment designs have shown a rapidly growing need for higher bandwidth interconnection between PCB modules. The fast evolving IC technology, with its multi-gigabit processing and driving capabilities, has made point-to-point backplane the topology of choice for many of today's new hardware systems. Both serial and parallel data structures can be supported with this topology. Lattice Semiconductor has introduced several IC products with multiple ports, each designed with Gbps backplane drive capability. These devices will be described later in this document. The remainder of this document will focus on PCB design aspects of the point-topoint backplane interconnection links.Point-to-Point Backplane Signal Path StructureThe typical point-to-point topology utilizes a simple, single-path interconnection structure that extends from a transmitting device on one card, across a backplane and second card, to a receiving device on another card. The physical path for such an interconnection is illustrated in Figure 3. Figure 3. Interconnection Link Physical StructureDevice Package Card PCB Backplane PCB Card PCB Device PackageConnectorConnectorThe point-to-point interconnection elements are all serially connected and provide a single signal path. Each element may be thought of as a transmission line segment. Ideally, by controlling and matching the characteristic impedance of each line segment, a uniform electrical signal path is created. Signals can then propagate the entire path length with no re?ections occurring. Adding a resistive termination at the receive device input, with value equal to the characteristic impedance of the line elements, would provide a distortionless data link with maximum bandwidth, between the transmit and receive devices. Each of the elements in Figure 3 can be broken down into of a number of sub-elements. The PCB elements for example, which provide the more signi?cant transmission line segments in the data path, consists of the sub-elements: metal traces, dielectric layers, ground plane layers, and (inter-layer) vias. Each of these sub-elements is a critical part of the signal path and can cause electrical line discontinuities and signal re?ections, if not properly designed. The design aspects of the elements and sub-elements contained in Figure 3 will be discussed in the following sections.2Lattice SemiconductorHigh-Speed PCB Design ConsiderationsAdvantages of Differential SignalingThe inherent system advantages of differential signal interconnection schemes are well known in all ?elds of electronic design. These advantages are especially important in high bandwidth, high-density hardware systems where very low error-rate data links are required. Differential signaling provides critically needed immunity to commonmode electrical noise that is present at signi?cant levels in most application systems. For example, using differential signaling avoids the classic &ground bounce& noise problem that is experienced with many high density ICs that use single-ended interfaces. It also provides higher noise margins, which lead to lower bit-error rates in digital data links. For these reasons, Lattice Semiconductors provides fully differential I/O interfaces, as will be described in the Device Introduction section. Differential signal interconnection methods should be used for all critical, high-speed interconnections.Board Design PracticesDifferential Trace DesignDifferential signal trace-pairs with controlled impedance can be arranged in a number of different con?gurations. Most common are the following four ?gures. Figure 4. Edge Coupled Microstrip (surface routing)W T H S WFigure 5. Edge Coupled Stripline (sandwiched between two reference planes)W T SWH1 H2Figure 6. Offset Edge Coupled Stripline (same as Figure 5, but not centered between reference planes)W T S H2 W H1Figure 7. Broadside Coupled Stripline (also referred to as Dual Stripline)100 ohm characteristic impedance has become an industry standard value for differential lines used for interconnection. This impedance level lends itself well to PCB structures and other components designs where controlled transmission line impedance must be provided.3Lattice SemiconductorHigh-Speed PCB Design ConsiderationsA 100 ohm differential line can be constructed with two 50 ohm single-ended lines of equal length. As the two line traces are brought near each other (as shown in Figure 4 through Figure 7), the ?eld coupling between the traces reduces the differential mode impedance of the line. To maintain 100 ohm differential impedance, the trace width must be reduced slightly. As a result the common mode impedance of each trace in a 100 ohm couple-trace differential pair will be slightly less than 50 ohms. Achieving a 100 ohm _differential impedance with a coupled pair of traces implies that the single ended impedance of Z0 ranges from 53 _to 60 ohm, with a coupling coef?cient typically ranging from 1-15%. The relationship between the common mode impedance Z0 and the differential impedance Zdiff is given by the expression Zdiff = 2 Z0 (1 - kb)/(1 + kb), where k is the trace coupling coef?cient. 50 ohm resistors, tied to ground, are normally used to terminate the 100 ohm differential lines. This provides the ideal differential line termination, which is most important since the data links use differential signals. The slight impedance mismatch that occurs in the common mode is usually of little consequence. Normally only noise and crosstalk signals occur in common mode.Common Mode Noise ToleranceIn order to prevent common mode noise from converting to differential mode noise, it is important to maintain the symmetry of the differential pair. Re?ections and impedance mismatch in the common mode will not affect the differential mode performance as long as the two modes can be kept relatively orthogonal. The loop area is de?ned as the area between the signal path and its return path. On differential traces, the signal is on one trace and the return is on the other trace. So the loop area is a function of how close the traces are routed together. If we are concerned about EMI emission and susceptibility, which is generally understood as a loop area concern, we must route the traces close together. The more closely we route them to each other, the smaller the loop area will be and the less EMI will be generated. One of the primary advantages of differential signals is the signal-to-noise ratio improvement that is obtained. Since the signal is one polarity on one trace and the other polarity on the other trace, the resulting signal at the receiving device is twice what the single-ended signal would be. Ideally common mode rejection at the receiving device is such that the receiving device only responds to the difference in signal level between the two traces. Since noise is typically in the common mode, it is rejected at the receiver and maintains a high differential signal-tonoise ratio. In order to have good common mode noise rejection, it is important that any noise that is present affects the signals on both traces equally. That is, if noise is coupled into one trace, an equal amount of noise must be coupled into the other trace. Then the common mode rejection capability of the receiving circuit will reject the noise. But if noise is coupled into one trace more strongly than into the other trace, the noise will appear as a differential mode signal to the receiver and be ampli?ed. The way to ensure that any noise is coupled equally into both traces is to route the two traces very close together. Then they will both be in the same noise environment.PCB Trace Impedance CalculationIn the past, calculation of the characteristic impedance for a printed circuit board trace was a complex, error prone process involving complicated calculations and approximation. Nomographs and simpli?ed formulas have been generated to simplify the design process, but are often inaccurate. The most accurate method available is a ?eld solver program (usually 2D, sometimes 3D), which solves Maxwell's equations directly over the volume of PCB under consideration using ?nite elements. These simulations can be veri?ed in hardware with a Time Domain Re?ectometer (TDR) measurement device. One example of a 2D ?eld solver program is the Si6000b program from Polar Instruments[1]. This is available as a shareware evaluation version, and can be downloaded for evaluation and testing on a workstation. Even using a ?eld solver, there are still uncertainties in the impedance calculation arising from variations in the effective dielectric constant in the glass ?ber, prepreg, and epoxy used in typical FR4 manufacturing. The average4Lattice SemiconductorHigh-Speed PCB Design Considerationsdielectric constant of FR4 varies from 4.2 to 4.5, depending on the material, exact location, and construction methods used. Veri?cation of the impedance on a PCB depends on actual measurements of typical copper traces. Some manufacturers use an auxiliary test section of a PCB called a coupon, which is a long rectangular test section of PCB with pads designed to accept probes from a TDR measuring instrument. It is not unknown for manufacturing errors to result in over-etching of the copper traces, with a resultant impedance error. Monitoring production quality with coupons can prevent this type of problem.Examples of PCB Trace Impedance CalculationAs a calculation example, we will ?nd the differential impedance for a pair of 6 mil traces in 1/2 ounce copper with 10 mil spacing that is on an FR4 substrate with a spacing of 5 mils above the ground plane (microstrip). The copper thickness (T) is 0.7 mils. Figure 8 shows the parameters. Note that this example uses a predecessor to the Polar Si6000b transmission line calculator product mentioned previously. Figure 8. Differential Microstrip example with Polar CITS25 Impedance Calculator ToolIn a typical FR4 PCB, there will be three types of differential pair routing encountered. For connections to surface mounted components, edge coupled microstrips may be needed, while connections between through-hole components or via pairs can use stripline and offset stripline. Dual stripline with broadside coupling should be avoided, since this con?guration is subject to differential noise coupling from the reference planes. Another problem with broadside coupling is that any asymmetry in the PCB manufacturing can result in an asymmetric trace impedance, causing mismatch in the effective electrical length, even if the physical lengths match exactly. Using edge couple it is easier to maintain symmetry. Vias, connectors, and component pads all introduce impedance discontinuities into the signal path, and this can be measured with TDR techniques. In order to avoid crosstalk, when laying out differential pair trace with spacing of value S, it is recommended to place pairs no closer than a distance of 3 S, and preferably a distance of 4 S if possible. This rule can be relaxed if a differential pair is only brie?y in proximity with another pair, such as at a connector or via layer switch.PCB Design Checklist1. Use 100 ohm_ differential impedance pairs on PCB. Controlled impedance lines should be speci?ed in PCB manufacture. 2. Match trace lengths in a pair with tolerance of 20% of the signal rise/fall time. 3. Use connectors that are designed and characterized at the highest data frequency. (Vendors should provide characterization and model data.)5Lattice SemiconductorHigh-Speed PCB Design Considerations4. Use stripline construction with ground/VDD planes above and below the differential pairs. 5. Use edge-coupled pairs in PCBs; try to avoid broadside coupled pairs. 6. Use 3 S separation rules between pairs to avoid crosstalk and excess coupling. Use offset stripline routing to get higher density of differential pairs with each routing layer running orthogonal to each other.PCB Layer Design (Board Stack-up)Multi-layer boards are a must in both daughter board and backplane design. The multiple metal layers facilitate high connection density, minimum crosstalk, and good ElectroMagnetic Compatibility (EMC). These factors are key to achieving good signal integrity for all the signal interconnections. Ideally, all signal layers should be separated from each other by ground or power planes (metal layers). This minimizes crosstalk and provides homogeneous transmission lines, with properly controlled characteristic impedance, between devices and other board components. Best performance is obtained when using dedicated ground and power plane layers that are continuous across the entire board area. When it is not feasible to provide ground or power planes between signal layers, great care must be taken to ensure signal line coupling is minimized. Orthogonal routing on adjacent signal layers minimizes coupling and should be used. CAD tools, which predict line coupling and signal crosstalk, can be very helpful in this type of design.ViasVias generally provide two purposes. One is used for mounting a through-hole component to a board. The second is to interconnect traces on different metal layers. Electrically, vias are often modeled as having an inductive and capacitive parasitic value. Smaller vias have lower capacitance. Short length, larger diameter vias have lower inductance. Both parasitic elements can have detrimental affects, but it is often the inductance parasitic element that provides an unexpected series impedance that creates problems.Lattice High-Speed I/O OfferingsLattice Semiconductor has introduced a series of silicon devices utilizing high-speed CML and LVDS serial interfaces that feature clock synthesis to embed data and clock in a serial stream in the transmitter monolithic clock and data recovery in the device receiver. These devices are listed in the following table. Table 1. Lattice Semiconductor ORCA FPGA, FPSC, ispXPGA and ispGDX2 High-Speed I/O DevicesDevice OR4E02/04/06 ORLI10G ORT8850H/L ORT82G5 ORT42G5 ORSO82G5 ORSO42G5 ORSPI4 ispXPGA ispGDX2 Description FPGA Family with high-speed differential I/Os 10 Gbps Line interface FPSC 6.8 Gbps Backplane FPSC (850 Mbps/ch) 29.6 Gbps Backplane FPSC (3.7 Gbps/ch) 14.8 Gbps Backplane FPSC (3.7 Gbps/ch) 21.6 Gbps SONET Backplane FPSC (2.7 Gbps/ch) 10.8 Gbps SONET Backplane FPSC (2.7 Gbps/ch) 14.8 Gbps Backplane (3.7 Gbps/ch) SERDES, OIF SPI4.2 Cores 450 MHz DDR (900 Mbits/s)X 2 FPSC 17 Gbps with SERDES FPGA (850 Mbps/ch) 13.6 Gbps with SERDES (850 Mbps/ch), 38 Gbps without SERDESThe ORT8850H/L, ORT82G5, ORT42G5, ORSO82G5, ORSO42G5 and ORSPI4 have integrated serializer and deserializer with CDR (Clock & Data Recovery) blocks, and also feature de-skew FIFO's that remove skew between multiple serial channels. This facilitates bonding of multiple serial channels for synchronized gigabit data transfers between chips, boards, racks, and systems. The data format is either SONET, with a subset of the full GR253 standard supported, or 8b/10b coding. The ORSPI4 also integrates dual 1.6 Gbps interfaces where each interface has 16 data lines running at double data rates to 450 MHz. (900 Mbps). The ORT82G5 supports eight6Lattice SemiconductorHigh-Speed PCB Design Considerationschannels, while the ORT42G5 and ORPSPI4 support four channels of serial data at rates up to 3.7 Gbps (2.96 Gbps per channel after 8b/10b decoding). The ORSO82G5 and ORSO42G5 support eight or four channels of serial data at rates up to 2.7 Gbps. At these high speeds Current Mode Logic (CML) I/O buffers are used. The ORLI10G provides a simpler high speed interface of 16 LVDS channels, without CDR or skew compensation. A synchronous, forward clocked interface can be used, with rates up to 850 Mbps. Great care must be taken by system designers to insure interconnection skews are properly controlled. This may impose speed and/or interconnection distance limits in some applications. The ispXPGA and ispGDX2 also have embedded SERDES blocks with CDR circuits. Both families support 8b/10b, 10b/12b and Source Synchronous mode. The encoding and decoding of 8b/10b blocks are not implemented in these devices.Integrated Input TerminationsLattice devices with high-speed serial LVDS inputs provide built in, programmable, 100 ohm differential line termination resistors. Integrating these resistors on-chip is very important in high-density packaging such as ball-grid arrays where an on-board resistor cannot be placed close to the device inputs, off-chip resistors signi?cantly reduce performance and increase the effects of re?ections. Lattice differential input terminations include center-tap access. The an example of the dedicated LVDS input for the ORT8850, ORLI10G and ORSPI4 is shown in Figure 9. Figure 9. LVDS Receiver TerminationOff-Chip On-Chip50 CTAP Pad + 0.01 F 50The center-tap is a virtual ground which may be ac-coupled to ground to increase receiver common mode noise immunity, as shown in the ?gure. Embedded LVDS output buffers also have on-chip 100 ohm_ differential terminations, but do not have a center tap. These terminations have been shown to reduce near-end crosstalk signi?cantly. ORCA Series 4 FPGAs and the programmable I/O buffers on the FPSCs, including the ORT8850H/L, ORT82G5, ORT42G5, ORSO82G5, ORSO42G5 and ORSPI4 also include special programmable LVDS drivers and receivers. This type of termination scheme is also available on the Series 4 general purpose FPGAs. These LVDS I/Os also include driver and receiver on-board 100 ohm _termination, but without the center tap. This termination resistor can also be disabled at the LVDS pair level. This scheme works well for receiver termination on a pin-by-pin basis, however it is programmable and can be implemented on the transmitters (drivers) also, thereby extending the reach of the LVDS signaling. ispXPGA and ispGDX2 Family devices do not provide internal input termination resistors and require external termination at receiver inputs.7Lattice SemiconductorHigh-Speed PCB Design ConsiderationsSpecial Design Considerations at 622/850 MbpsLine Loss and Impedance DiscontinuitiesAt data rates of 622 Mbits and higher, it should be realized that the skin effect is extremely important for signal conduction. Small traces on a PCB (like 4 or 5 mil widths) will exhibit signi?cant signal attenuation over long distances. Over-etching of a PCB can produce narrow traces that can reduce the signal amplitude available at the receiver. The end result is that, to the designer, the interconnection between devices resembles a badly designed low pass ?lter, with attenuation, which increases with frequency. For this reason, the longer the backplane, the wider the signal traces should be made. Long backplane traces (more than 20 in.) should have trace widths of 10 or 12 mils. Connectors and vias in the signal path introduce discontinuities that resemble lumped elements in an electrical model. One way to take this into account is to perform SPICE simulation of the backplane system using lossy transmission line models, and manufacturer supplied models of the connectors, signal drivers, and signal receivers.High-Speed ConnectorsMany connectors have been tried and discarded in high-speed applications. Surprisingly, some out-dated connector designs have been found to be usable at gigabit data rates. An example of this is the venerable DB-9 connector, which is sometimes found in Fibre Channel products. A more modern approach is to use controlled impedance connectors speci?cally designed for high-speed data, where abundant ground connections and shielding features reduce the noise and impedance discontinuities seen in older connectors. Examples of these are the AMP Mictor connectors, and the 2mm standard backplane connector families that are available from various suppliers for the 2 mm hard metric backplane standard (such as the AMP HS3 connector). These are available in both vertical and horizontal con?gurations. Several evaluation cards use an unshielded 2 mm connector (AMP ), and this provides good performance for driving twinax cables up to a distance of 65 ft (at 622 Mbps), error free.Device PackagingTransmitter and receiver device packaging parasitic reactances are important to signal integrity. Wire-bond and package substrate inductance and capacitance should be included in device SPICE models. Simulation of package parasitics has shown that impedance transformation and signal re?ections can result at higher frequencies. Pin location in larger packages can have a signi?cant impact on the parasitic values of the model. Internal receiving device terminations, such as provided in Lattice LVDS and CML buffers, were found to have superior performance when compared to receivers which require external resistor termination components.High-Speed Copper CablesHigh-performance cables generally far outperform PCB interconnections in terms of bandwidth and signal attenuation. This is because a high-performance cable uses expanded Te?on dielectric (PTFE); silver-plated conductors, and low-loss shielding material. These cables are also engineered with a conductor geometry that is usually extremely close to the optimal position for the desired bandwidth and characteristic impedance. One cable that performs extremely well is the W. L. Gore DXSN2112 Eye-opener Plus cable. This high performance cable is engineered speci?cally for data transmission at 622 Mbps. Unfortunately, this cable is not easily assembled with connectors using simple hand tools. Complete cables with connectors may be ordered directly from Gore. The cable assembly that matches the 2 mm backplane connector (AMP ) on many Lattice evaluation cards is Gore part number 2MMA3106. Another cabling example is included with the Lattice ORT8850 evaluation boards. In this case, connections through a path including dipswitches, backplane connector and 65 ft of Gore DXSN2112 cable were error free at 622 Mbps. When routing the signal through Motorola LVPECL buffers and receivers with Gore DXN2151 cable, this was seen to be error free at a distance of up to 90 ft. Minimal reductions in the distances are expected at the maximum 850 Mbps for the ORT8850.8Lattice SemiconductorHigh-Speed PCB Design ConsiderationsAdditional information on copper cable can be found in the “Transmission of High-Speed Serial Signals over Common Cable Media” Application Note (Technical Note TN1066).Special Design Considerations at 2.5/3.125/3.7 GbpsAt 2.5/3.125/3.7 Gbps, the design problem becomes substantially more dif?cult. The higher copper and dielectric losses occurring at these frequencies, generally limit PCB interconnection lengths to about 40 inches. The greatest care in all aspects of PCB layer and layout design is required at these frequencies.Board Thickness and ViasBackplane thickness and via design can have signi?cant affects on signal integrity. A backplane thickness of less than 0.200 inches generally gives the best results. Vias used to interconnect between layers create transmission line discontinuities. PCB designs with high-speed signal traces should be routed on as few layers as possible, thus limiting the number of vias. Thicker boards normally have longer length vias that can cause larger discontinuities, and degrade the signals. Longer vias connecting signal layers that are close together will appear as transmission line stubs, attached to the signal path. Stubs have been shown to have a very detrimental affect on signal integrity. Buried vias can be used to reduce this problem in thicker boards, but manufacturing costs for this technology can be prohibitive. Ideally, each signal path through the backplane should be kept on the same layer.Board MaterialFR4 dielectric loss becomes a signi?cant design factor above 2 Gbps. Another design option is to use low-loss dielectric PCB material, such as Rogers 4350, GETEK, or ARLON. This is approximately double the cost of FR4 PCB material, but can provide increased eye-opening performance when longer trace interconn as shown from data collected by AMP Inc. Figure 10 gauges the improvement in signal eye opening at 2.4 Gbps, as lower loss materials are used. It can be seen from the ?gure that FR-4 material may deliver a satisfactory eye opening. It might then be the preferred low cost solution for a particular application. Figure 10. System Eye Patterns (2.4Gbs) vs. PCB Dielectric Material9??Lattice SemiconductorHigh-Speed PCB Design ConsiderationsSpecial Layout Considerations for ORT/ORSO82G5, ORT/ORSO42G5, and ORSPI4 SERDES DevicesPCB Routing and Board Stack-upRouting on inner and outer layers have impedance changes inversely proportional to line width and directly proportional to height. The rate of change with trace height above GND is much slower in a stripline signal compared with a microstrip signal. Stripline has considerably higher (typically one and a half times) propagation times than that of microstrip. A stripline route has a signal sandwiched by FR-4 material and a microstrip has one conductor open to air. A microstrip route is coupled to the ground plane below, which reduces EMI by absorbing some of the electromagnetic ?eld lines. In stripline routing, all of the electromagnetic ?eld lines are coupled to the above and below reference planes thereby reducing EMI signi?cantly. To achieve the same line impedance, the dielectric distance must be greater in stripline layouts compared with microstrip layouts. A higher effective dielectric constant of stripline is due to the sandwich effect as compared to microstrip. Controlled impedance lines stripline traces are thicker than microstrip and it is also dif?cult to achieve accurate 100ohm differential impedance on inner layer routing. The before mentioned trade-offs between the microstrip and stripline routing play a vital role in determining total system jitter and signal strength characteristics. Experimentation has shown that the SERDES HDIN receiver input signals can be adequately routed using stripline without any critical system penalties. However, HDOUT transmit outputs routed on 1 ounce copper weight, 10-mil wide microstrip, provided the most optimal performance and signal characteristics versus experiments with stripline routing. Experimental results have shown maximum eye openings and low jitter exhibited with microstrip. In addition, routing the HDIN and HDOUT signals on the device-side outer layer offers additional bene?ts as it also reduces discontinuities from additional vias before any potential discontinuities at the on-board connectors. Consequently, it is recommended to route these traces, especially for HDOUT, on this outer layer. Use the following guidelines when routing HDIN and HDOUT CML signals. ? ? ? ? ? ? ? ? ? ? ? ? ? ? W=width of a single trace in a differential pair S=space between two traces of a differential pair D=space between two adjacent differential pairs H=Dielectric thickness (Refer?to?Figure?4) The space between differential traces (S) should be S = 3H as soon as physically possible as the traceleaves the device pin. This aids in minimizing re?ection noise. Make sure Distance between adjacent Channel pairs & 3S to minimize the crosstalk between the two differential pairs. Avoid running adjacent channels a long distance in parallel. Keep the distance between the differential traces (S) constant over the entire trace length. All channels need to be 100-ohm differential impedance matched transmission lines. FR-4 Microstrip routed HDOUT and HDIN signals should be W= 10-mil minimum, 1-ounce copper weight. To avoid signal discontinuities, arcs or 45-degree traces are recommended instead of 90-degree angle turns. Keep the length of the two differential traces the same to minimize the skew and phase difference. Avoid using multiple vias. Blind vias help reduce stub effect discontinuities.Other layout suggestions ? VDDRX, VDDTX, VDDAUX can be connected together and must be properly decoupled and isolated for digital noise. Use of a digital noise ?lter such as a Panasonic- ELK-E100-FA is suggested. ? VDDGB should be properly decoupled and isolated from digital noise. Use of a digital noise ?lter such as a Panasonic- ELK-E100-FA is suggested.10Lattice SemiconductorHigh-Speed PCB Design Considerations? VDDIB and VDDOB should be decoupled as close as physically possible to the device and minimize the use of vias. ? Decoupling and bypass suggestions can be found in the ORT/ORSO82G5/42G5 datasheet.High-Speed Connectors and IC PackagingAbove 1 Gbps, connectors speci?cally designed for higher frequencies are recommended. Several new controlled impedance backplane connectors have become available, with data-rate capabilities in excess of 3 Gbps. A popular example is the Tyco Z-Pack HD-Zd 2-mm pitch family, which has been carefully characterized and modeled at frequencies up to 5 GHz. This class of connector provides some additional shielding bene?ts, which can aid the designer in controlling system noise and crosstalk. The IC packaging comments of the previous section apply here as well. SPICE modeling of the package parasitics is the best way to evaluate effects on system performance, since measurement probes typically have parasitics equal to or greater than the packages used today. Care should be taken to insure that the vendor provided package models are valid through the intended frequency of operation.Pre-EmphasisSignal pre-emphasis is a means of compensating for the increased PCB loss that occurs at higher frequencies. A simple algorithm can be employed in the line driver to increase transmitted signal amplitude, whenever the data patterns have transitions (and therefore higher frequency content). This function is provided by the ORT82G5 SERDES CML drivers [4]. For longer PCB interconnection trace lengths, a signi?cant increase in eye opening often results [3]. Use of the preemphasis can extend the maximum useable interconnection length, or allow the use of lower cost (greater loss) material and components, in system design. A more detailed description of the pre-emphasis feature may be found in Reference [4].ConclusionPCB backplane interconnections with serial data rates up to 3.7 Gbps are possible with today's technology. Lattice FPSC devices allow easy system design at rates to 850 Mbps through the ORT8850H/L serial or ORLI10G parallel interface. Increased performance with rates up to 3.7 Gbps is achievable with the ORT82G5, but greater care is needed in the PCB design. Systems running at these higher data rates may bene?t from the use of transmitter preemphasis, controlled impedance connectors, and low loss PCB dielectric materials.References1. Si6000b ?eld solving impedance calculator (downloadable demo version): http://www.polarinstruments.com/ 2. W.L. Gore high-performance interconnect products: http://goreelectronics.com/ 3. ORT82G5 High Speed Backplane Measurements, Lattice Tech Note TN1027 4. ORCA ORT82G5 and ORT42G5 Data Sheet 5. ORCA ORSO82G5 and ORSO42G5 Data Sheet11
All rights reserved Powered by
www.tceic.com
copyright &copyright 。文档资料库内容来自网络，如有侵犯请联系客服。}